Welcome to minnesota’s documentation!¶
Contents:
Introduction¶
The mn
package is a collection of HDL cores written in
myhdl. The mn
package is more than just a collection of
cores it is also a framework for creating complex digital
circuits. The mn
package also includes a complete test
suite.
The mn
package is divided into three main subpackages:
- system
- models
- cores
System¶
The system subpackage contains the [interfaces]() and other useful tools to assist in building complex digital designs.
Models¶
This subpackage contains various models used for development and verification.
Cores¶
This subpackage contains the core implementations.
Cores¶
The following is a list of currently implemented cores.
FIFO¶
Various synchronous and asynchronous FIFO implementations.
fpgalink¶
This is a MyHDL implementation of the HDL for the fpgalink project. The fpgalink HDL core can be instantiated into a design:
For simulation and verification the fpgalink interface can be stimulated using the FX2 model and high-level access functions:
The following is a pictorial of the verification environment .
For more information on the [fpgalink]() software, firmware, and general design information see [makestuff]().
usbp¶
USB Peripheral, this is another Cypress FX2 controller interface, this has two interfaces a “control” interface and a “streaming” interface. This FX2 interface is intended to work with the [fx2 firmware]() that configures the controller as a USB CDC/ACM device (virtual serial port). The [fx2 firmware]() also has a couple vendor unique commands that can be sent using the pyusb (or other low-level USB interfaces like libusb). The Python version of the host software (including firmware) can be retrieved via pip
>> pip install usbp
>>> import usbp
>>> import serial
One of the tricky items with USB devices is setting the permissions correctly. On a linux system to set the …
spi¶
This is a generic SPI controller.
vga¶
VGA controller.
The following are the examples available in the examples directory.
Xess Xula(2)¶
- binary hello (blinky)
- VGA (TBC)
Digilent Nexys¶
- binary hello (blinky)
- fpgalink
- usbp
Digilent Atlys¶
- binary hello (blinky)
- fpgalink (TBC)
- usbp (TBC)
Digilent Zybo¶
- binary hello (blinky)
Open-Source UFO-400¶
- binary hello (blinky)
- usbp
DSPtronics Signa-X1 (sx1)¶
binary hello (blinky)
fpgalink
usbp
- audio examples
- audio echo (TBC)
- audio streaming (TBC)