Cores¶
The following is a list of currently implemented cores.
FIFO¶
Various synchronous and asynchronous FIFO implementations.
fpgalink¶
This is a MyHDL implementation of the HDL for the fpgalink project. The fpgalink HDL core can be instantiated into a design:
For simulation and verification the fpgalink interface can be stimulated using the FX2 model and high-level access functions:
The following is a pictorial of the verification environment .
For more information on the [fpgalink]() software, firmware, and general design information see [makestuff]().
usbp¶
USB Peripheral, this is another Cypress FX2 controller interface, this has two interfaces a “control” interface and a “streaming” interface. This FX2 interface is intended to work with the [fx2 firmware]() that configures the controller as a USB CDC/ACM device (virtual serial port). The [fx2 firmware]() also has a couple vendor unique commands that can be sent using the pyusb (or other low-level USB interfaces like libusb). The Python version of the host software (including firmware) can be retrieved via pip
>> pip install usbp
>>> import usbp
>>> import serial
One of the tricky items with USB devices is setting the permissions correctly. On a linux system to set the …
spi¶
This is a generic SPI controller.
vga¶
VGA controller.